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Algorithm-Structured Computer Arrays and Networks. by Leonard Uhr, Werner Rheinboldt

By Leonard Uhr, Werner Rheinboldt

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Additional resources for Algorithm-Structured Computer Arrays and Networks. Architectures and Processes for Images, Percepts, Models, Information

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This means that the instructions' names must be stored as part of the conditional, and when the branch is to an instruction that is not 24 1 Conventional and Distributed Computers simply one greater than the previous instruction, that different instruction's name (number) must be loaded (just like a fetch) into the instruction counter. Consider the following statement: IF c ( a+b+c +d+e+f +g ) / z > t THEN ν := t r u e and see whether you can spell out all its tedious details. ) This is about all there is to it!

Gregory and McReynolds (1963) describe the hardware in some detail. A prototype was built at Westinghouse and brought to the University of Illinois after Slotnick moved there. But there appear to be no reports describing results of programs run on it. Figure 3 shows a portion of the array of processors in SOLOMON I. CENTRAL CONTROL- PROGRAM "STORAGE I BRANCHING LEVELS " ;; ι ΡΕ " ; ΡΕ - ~ ~^ PE Fig. 3 The SOLOMON I controller and processors (PEs). [From Slotnick et al. (1962). ] Figure 4 gives the block diagram for a processor.

00 The Univac actually gave poorer throughput with four CPUs, because of memory access conflicts. Larger local memories would reduce these conflicts. But these CPUs are already very expensive additions to very expensive systems. These computers were also designed to "time share"—that is, to execute a number of programs at the same time, the processor doing a bit of work on one, then going to the next, and so on, so that each program moves forward, although at the level of the processors only one program is being executed by each processor at each "slice" of time.

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